Inkjet Printer Driver Circuit Architecture

ABSTRACT

A driver circuit for driving an array of inkjet printer actuators, comprising a serial input ( 15, 20 ) for receiving serial print data, a register ( 25, 26 ) for storing the print data in the form of event and event timing data pairs, a parallel output ( 30, 32 ) for outputting event data and control circuitry ( 42, 48 ) for controlling the timing of output of event data according to corresponding event timing data. The driver circuit preferably comprises a programmable part ( 10 ) and a fixed part ( 11, 12, 13, 14 ), in which the programmable part stores selectable pre-programmed waveforms and outputs event and time data pairs to the fixed circuit part, which controls the timing of output of the event data.

FIELD OF THE INVENTION

This invention relates to a new architecture for an inkjet printerdriver chip capable of very flexible waveform definition andline-by-line trim capability.

BACKGROUND TO THE INVENTION

Piezo-electric actuators typically comprise two electrodes between whichis an element formed from a piezo material such as PZT (Lead ZirconateTitanate). The electrodes apply an electric field to the material intois induced a small mechanical strain due to the piezo effect. In thefield of piezo-electric inkjet printing, one or more smallpiezo-electric actuators cause the volume of an ink chamber to changemomentarily, causing a pressure change within the chamber, that, whenlarge enough, can result in the ejection of a droplet of ink through anozzle communicating with the chamber, the droplet being ejected towardthe printing paper or substrate. Often the piezo-actuators themselvesform one or more of the side walls of the chamber.

In the field of high quality drop-on-demand inkjet printing, typicallyan array of inkjets are configured side by side and traverse the paperor substrate to print a swathe of ink. It is desirable that all inkjetsfire substantially the same volume droplets of ink at substantially thesame velocity, especially when such a swathe is to be printed in aconstant colour or density. Variations in velocity can cause thedroplets to land slightly displaced from the intended position, whilstvariations in volume cause variations in print density. The human eye isvery sensitive at perceiving any variations. Although each inkjet isnominally identical, such variation can be caused by a variety offactors.

Piezo actuators are typically driven by driver circuits which apply aparticular voltage across the electrodes causing the actuator to move.An example of a driver circuit is HV3418 available from Supertex Inc.,which is a 64-channel serial-to-parallel converter with high voltagepush-pull outputs. That circuit has a 64-bit shift register, 64 latchesand control logic to perform polarity select and blanking of theoutputs.

A problem with existing drivers is that they have no capability orlimited ability to control actuators individually, and especially theyare not able to incorporate fine adjustments to individual actuators toaccount for factors that give rise to variations between individualnozzles, such as variations that arise from normal manufacturingtolerances. To the extent that existing drivers may allow limitedcapability to control actuators individually, many aspects of suchcontrol are hardwired into the driver, limiting the ease with which suchdrivers can be adapted to the requirements of rapidly evolving printheaddesign.

SUMMARY OF THE INVENTION

In accordance with the present invention, a driver circuit is providedfor driving an array of inkjet printer actuators. The circuit has aserial input for receiving serial print data, at least one register forstoring the print data in the form of event and event timing data pairs,and a parallel output for outputting event data. Control circuitrycontrols the timing of output of event data according to correspondingevent timing data.

In accordance with another aspect of the invention, a driver circuit fordriving an array of inkjet printer actuators is provided whichcomprises, together and individually, first and second circuit parts.The first part is programmable and has an input for receiving printdata, storage means for storing selectable pre-programmed waveforms inthe form of event and timing data, and an output for outputting eventand time data pairs based upon the print data and the pre-programmedwaveforms. The second part has a register for receiving and storingevent and time data pairs, a parallel output for outputting event data,and control circuitry for controlling the timing of output of event dataaccording to corresponding event timing data.

A preferred embodiment of the invention is now described, by way ofexample only, with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a driver architecture in accordance withthe preferred embodiment of the invention.

FIG. 2 shows the internal architecture of the driver ASIC of FIG. 1

FIG. 3 is a block diagram illustrating a driver and output stage for asingle channel.

FIG. 4 is a time diagram illustrating a typical waveform for firing anindividual inkjet channel actuator; and

FIG. 5 illustrates a conceptual model of FPGA logic for a singlechannel.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the overall architecture of a driver in accordance with thepreferred embodiment. It consists of a field programmable gate array(FPGA) 10 collected to four high voltage drivers 11, 12, 13, 14, eachimplemented in an application specific integrated circuit (ASIC). TheFPGA 10 has a data input 15 to receive hexadecimal data representing theimage to be printed. The FPGA 10 converts this data into individualpixel data for line-by-line printing by the inkjet printer. Theindividual pixel data is coded in a coding scheme based on data pairscomprising Event and Event_time values. An Event is an instruction tochange an actuator driver state. For example to change from pull-down topull-up with a particular slew rate and voltage clipping level attached.An Event_time is a binary coded time at which this is to happen. TheEvent_time can be coded to 10 ns resolution. The data pairs aredelivered to the various driver ASICs 11 to 14. Since waveforms to beapplied to individual actuator electrode are individually specified by aseries of such Event and Event_time pairs, the logical structure of, andrelationship between the group of waveforms applied to an array ofactuators as a whole, is substantially defined and controlled by theFPGA and not the driver ASICs. Therefore, by way of reprogramming theFPGA, the architecture has an inherent adaptability to changing waveformrequirements and to differing methods of compensating variations thatoccur between nozzles.

Referring to FIG. 2, the internal structure of each ASIC 11 to 14 indriver mode is illustrated. Each ASIC comprises an input 20 to receivethe Event and Event_time pairs from the FPGA 10. The input 20 ispreferably four bits wide at 300 MHz, but could have 12 bits at 100 MHz(an optional low voltage differential signalling (LVDS) andserializer/deserializer (SERDES) circuit 21 is shown, depending on theselected bus width). The data is input into an internal bus 22 through2-stage memory/register loader logic 23. Connected to the bus 22 is a32×17 bit lookup table memory 24 and a 24-bit 66-stage shift register25. Also coupled to the register loader logic 23 are a control register28 and a 3×14 FIFO timer/buffer 29.

Logically, data from input 20 passes through register/memory loaderlogic 23 to feed shift register 25, which acts as a serial-to-parallelconverter. (Together therefore, elements 23 and 25 comprise a 68-longshift register.) Shift register 25 is connected in parallel to a bank of66 identical 24-wide by 3-deep FIFO registers 26. The bank of registers26 is in turn connected in parallel to a 66-bit-wide high voltage outputstage 30, which is connected to 66 high-voltage output pads 32.

In operation, data words consisting of a seven bit Event_time and a fivebit Event are clocked into the data bus 22. The five bit Event code isexpanded to 17 bits via the lookup table 24 by adding voltage trim (6bits), slew rate trim (8 bits) and an action code (3 bits). The trimformula provides data to control drop volume and velocity independentlyfor each output nozzle and allows each trim setting to be expanded to anappropriate combination of slew rate and voltage trim to give higherprecision.

The expanded input data is shifted into the 66-stage register 25. Datain register 25 advances until it is aligned with output pads 32 and isframed by a synchronisation input which is active every 68 clocks. It isthen transferred into the bank of FIFO registers 26

With every synchronisation pulse, a complete set of data is ready to beloaded by the bank of FIFO registers 26, which internally contains oneidentical element 40 for each output pin. The structure of each of theseFIFOs is shown in greater detail in FIG. 3.

Before describing the FIFOs in greater detail, reference is made toelements shown in the upper-left hand portion of ASIC 11, in FIG. 2.Coupled to the memory/register loader logic 23 are shown a 3-stagecontrol register 28 and a 3-stage A/D input select timer/buffer. Theformer is optional. The latter is connected to a 66-to-1 analogmultiplexer (preferably a differential analog multiplexer), which has a66-bit-wide input from the output stage 30 and an analog output to a8-bit 25 Msamples/second A/D converter 36. The A/D converter 36 providesa digital feedback signal to the FPGA 10.

In operation of these elements, the A/D input select timer/buffer 29controls selection in turn of each of the 66 analog outputs from theoutput stage 30 for connection to the A/D converter 36. When each outputis in turn connected to the A/D converter, a digital reading of thatoutput is provided on output 38 for analysis by the FPGA 10, or for FPGA10 to pass to other data processing equipment for analysis. This isparticularly useful for features such as temperature measurement, oranalysis of reflections in the inkjet printer actuators (as described inco-pending patent application GB0506307.8 “Improved Piezo-Electric InkJet Driver with Active and Passive Impedance Adaptation and MotionFeedbak Control and Monitoring”) or for analysis of actuator resonantfrequencies or associated resonant Q-factors (as described in co-pendingpatent application GB0506302.9 “Simplified method for establishing dropvolume and drop velocity correction requirements in drop-on-demand inkjet printing apparatus”).

FIG. 3 shows an individual cell 40 containing registers 41 a, 41 b and41 c. One cell receives 24 bits (the seven bit event time and the 17bits of expanded event code). The seven bits of event time are clockedthrough a seven-bit delay counter portion 42 of the FIFO cell 40. The 17bits of expanded event data are clocked into a 6 bit clip level portion43, an 8-bit output current portion 44, a clamp enable portion 45 andfirst and second voltage rail control bits 46 and 47. These variousportions of the output to the FIFO cell 40 are coupled to D-to-Aconverters 50 and 51, a clamp enable line 52 and a two-bit demultiplexer53 respectively, all contained within output stage 49. These variouselements are in turn coupled to an output analog control block 55, alsowithin output stage 49.

Control block 55 is coupled to pull-up and pull-down transistors 57 and58 respectively, these transistors being connected between a 65vpositive supply rail and ground. Transistors 57 and 58 have amid-connection which is connected to an output pad 32. Also connected tooutput pad 32 are pull-mid transistors 62 and 63, which are coupled to amid-rail voltage of 32.5 volts.

In operation, six bits of clip level data are clocked through FIFOportion 43 into D-to-A converter 50, and the analog equivalent isapplied by control block 55 to transistors 57 and 58 to cause a selectedvoltage to be applied to pad 32. Similarly, 8 bits of slew rate controlare clocked through FIFO portion 44 and D-to-A converter 51, and outputanalog control block 55 causes a controlled slew rate to be applied tovoltage transition of pad 32. Control bits 45, 46 and 47 determine theswitching state to which pad 32 needs to be switched, e.g. high, low,mid rail and high-impedance. For each event, a delay counter 42 recordsthe precise time at which the transition is to occur.

Coupled to the delay counters 42 is a further FIFO controller 48 whichmaintains circular read and write pointers to the three corresponding24-bit register arrays 41 a, 41 b & 41 c. The lower seven bits of eachregister are “live” down-counters continually counting down. When thecounter at the head of the queue expires, it allows the read pointer toadvance, and new data to be read out of the associated registers freeingthem to buffer more data on the next sync pulse. When the FIFO isimplemented as a circular buffer as described, the data in registers 41a, 41 b and 41 c does not need to be physically moved during its logicalprogression through the FIFO. (As an alternative, however, the data canbe parallel shifted through the FIFO so that register 41 a alwaysreceives the serial data and register 41 c always outputs the paralleldata to the output pads 32.)

Whenever the FIFO read pointer advances, it allows new data to bepresented to the output stage. The code tells the output buffers whichvoltage rail to pull toward, or whether to turn all buffers off for ahigh impendence state. As already mentioned, eight bits are binary codesfor current drive strength or slew rate control, and six bits are forvoltage clipping level. Each transition can therefore be controlled inits start time, slew rate and final voltage. A further “clamp enable”signal causes an output to turn on very hard to clamp inactiveelectrodes to ground in shared-wall actuators.

The relative allocation and total number of bits for clipping level andslew rate are not essential, and different allocations can be designed,depending on factors such as which of two voltage trim options aredecided upon (see below).

FIG. 4 shows how a complete ink jet actuator pulse 100 can be encoded.In this case a pulse is shown requiring three Events: a pull-up event101 at time delay (n), a pull-down event 102 at time delay (n+1); and aclamp event 103 at time delay (n+2). Each Event happens at the time ofthe Sync pulse which transmitted it, delayed by the value of the 7-bitdelay counter. Since the maximum delay is nearly twice the intervalbetween sync pulses, an Event notionally belonging to one sync periodcan be delayed into the next (for example event 102), allowing up to twoqueued events to occur within the same sync period as shown (one purposeof the FIFO is to decouple the rate of input data from the rate ofoutput data to allow this to happen). The coding method has theadvantage that it cannot accumulate errors as might be the case withsimple run-length coding. This makes the coding method quite robust in anoisy environment.

FIG. 5 shows a conceptual model of example FPGA logic for one of each ofthe 66 channels to be controlled. (Although the resources shown in FIG.5 are for a single channel, in reality the memory storage and much ofthe logic can be shared on a time division basis.) Data bus 60 shiftsgreyscale print data in from a previous identical circuit and outputsthe same data on the next clock edge to a successive channel via databus 61. If the data so shifted is correctly aligned so that it is theprint data for the particular channel shown, then the print data istransferred to channel data register 62. The print data in combinationwith print cycle identifying signal 63 and optional greyscales subdropcounter 65 determines which waveform of a number of alternativewaveforms to apply to the actuator. Shared memory block 64 stores threewaveform definitions in the form of Event/RunLength pairs, where Eventis typically in the same format as described previously in relation toEvent/EventTime pairs.

A number of alternative waveform definitions can be stored. For examplein so-called shared-wall architecture print heads, only one third ofactuators can be fired at any one time. This requires each actuatorelectrode to be driven by one of three alternative waveforms. A firstpossible waveform, the firing waveform is used when a channel is at apoint in a complete firing cycle where it can eject a droplet (providedthe print data demands ejection of a droplet). A second possiblewaveform, the non-firing waveform is used when a channel is at a pointin a complete firing cycle where it may eject a droplet but the printdata does not demand ejection of a droplet. A third possible waveform,the adjacent waveform, is used when a channel is at a point in acomplete firing cycle where it is never required to eject a droplet butis physically adjacent to one which may.

In binary printing the print data directly controls whether the firingor non-firing waveform is alternatively chosen for a channel that mayconditionally eject a droplet. In greyscale printing, a binary greyscalevalue determines how many sub-drops (for example between 0 and 15) areejected in rapid succession. The function of subdrop counter 65 is tocount the number of sub-drop ejected.

In the example of FIG. 5, three blocks of Event/RunLength pairs arestored in sequential memory A run-length group can comprise a constantnumber of Event/RunLength pairs (e.g. (2, 3, 4 or 5 or more) needed tocode each successive sub-drop waveform). A combination of greyscale dataand cycle is used to determine which of the three alternative waveformsto apply in any given sub-drop period. The necessity to be able toswitch waveform selection between sub-drop periods means that run-lengthgroups preferably always start and finish at sub-drop boundaries or atthe same point in time during a sub-drop period. This requirement leadsto some inefficiency, purely from a waveform encoding perspective, sinceadditional Event/RunLength pairs are required to “top and tail” eachsub-drop period (except where a waveform would already have had an Eventon a sub-drop boundary). To avoid unnecessary bandwidth burden on thedata channel 20, from the FPGA to the driver ASIC, the RunLengthqueue/combiner pipe shown in FIG. 5 identifies when two successiveEvent/RunLength pairs code the same Event and combines them by addingthe run-lengths. An adder/subtractor 67 then “chips away at” theresulting run-length by subtracting 68 every Sync pulse time. Whilethere remains more than value 128 as numeric remainder in the run lengthregister, the same Event is repeatedly output into the Event data shiftregister with EventTime set to zero. When there is less than 128remaining, the numeric remainder is output as EventTime with the nextEvent in the queue and the queue is advanced.

This mechanism produces the Event/EventTime data expected by the driverASIC, and this data is loaded into Event Data Shift Register 68 whichforms part of a parallel-to-serial converter shift register along withthe other identical channel circuits (not shown) and from which data canbe shifted out to the driver ASIC.

It will, of course, be understood that the embodiment described has beengiven by way of example only, and that numerous and varied modificationscan be made within the scope of the invention.

1. A driver circuit for driving an array of inkjet printer actuators,comprising: a serial input for receiving serial print data; a registerfor storing the print data in the form of event and event timing datapairs; a parallel output for outputting event data; and controlcircuitry for controlling the timing of output of event data accordingto corresponding event timing data.
 2. A driver circuit in accordancewith claim 1, further comprising a lookup memory for storing trim datafor individual actuators.
 3. A driver circuit in accordance with claim2, wherein trim data for a given actuator is combined with event datafor that actuator for adjustment of the event data each time event datais to be output to that actuator.
 4. A driver circuit in accordance withclaim 1, comprising a plurality of registers in a parallelfirst-in-first-out configuration for outputting one set of event data inparallel from one register while inputting a later set of event data inseries to another register.
 5. A driver circuit in accordance with claim4, comprising at least three registers in a parallel first-in-first-outconfiguration, wherein, in a given sync cycle, one register receivesevent data in series, one register stores event data and one registeroutputs event data in parallel.
 6. A driver circuit in accordance withclaim 5, comprising a FIFO controller for maintaining circular read andwrite pointers to the at least three registers, for selectively enablingand disabling read and write modes of the registers.
 7. A driver circuitin accordance with claim 5, further comprising a synchronization inputfor receiving a sync pulse each n clock cycles, wherein the event timingdata is arranged to control timing of event outputs within a rangegreater than n, such that event data for different actuators may beoutput from different registers in a given sync cycle.
 8. A drivercircuit in accordance with claim 1, wherein the parallel outputcomprises a channel for each actuator, each channel comprising aparallel output and at least one digital-to-analog (D/A) converter forconverting the parallel channel output to an analog signal for drivingat least one piezo-electric actuator of the array of ink jet actuators.9. A driver circuit in accordance with claim 8, wherein each channelcomprises at least first and second parallel outputs and at least firstand second D/A converters, the first parallel output and D/A converterfor converting actuator clip level data and the second parallel outputand D/A converter for converting actuator current or slew rate.
 10. Adriver circuit in accordance with claim 8, further comprising ademultiplexer for demultiplexing predetermined output bits of eachchannel to provide control signals for that channel.
 11. A drivercircuit in accordance with claim 10, wherein the control signals includesignals to drive a channel output to one of high-voltage, low-voltageand high-impedance.
 12. A driver circuit in accordance with claim 11,wherein the control signals further include a signal to drive thechannel output to at least one intermediate voltage between the high andlow voltages.
 13. A driver circuit for driving an array of inkjetprinter actuators, comprising: a programmable circuit part and a fixedcircuit part, the programmable circuit part comprising an input forreceiving print data, storage means for storing selectablepre-programmed waveforms in the form of event and timing data, and anoutput for outputting event and time data pairs based upon the printdata and the pre-programmed waveforms; and the fixed circuit partcomprising a register for receiving and storing the event and time datapairs, a parallel output for outputting event data, and controlcircuitry for controlling the timing of output of event data accordingto corresponding event timing data.
 14. A driver circuit for driving anarray of inkjet printer actuators, comprising: a programmable circuitpart comprising an input for receiving print data; storage means forstoring selectable pre-programmed waveforms in the form of event andtiming data; and an output for outputting event and time data pairsbased upon the print data and the pre-programmed waveforms.
 15. A drivercircuit for driving an array of inkjet printer actuators, comprising; aregister for receiving and storing event and time data pairs; a paralleloutput for outputting event data; and control circuitry for controllingthe timing of output of event data according to corresponding eventtiming data.